This patent application includes microfiche Appendices A and B which are a part of the present disclosure, and which are incorporated by reference herein in their entirety. These Appendices consist of a total of 6 sheets that contain a total of 585 frames. Appendices A and B include listings of computer programs and related data including source code in the languages C++ and Perl for implementing runset generator that automatically generates DRC rules in one embodiment of this invention as described more completely below.
A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
A computer programmed with appropriate software (called layout verification tool) is normally used to verify that a design of an integrated circuit (IC) chip conforms to certain predetermined tolerances that are required by a process to be used in fabricating the chip. Examples of such a layout verification tool include (1) HERCULES software available from Avant! Corporation, 46871 Bayside Parkway, Fremont, Calif. 94538, Tel 510.413.8000, and Web site www.avanticorp.com, (2) VAMPIRE software available from Cadence Design Systems, Inc, 555 River Oaks Parkway, San Jose, Calif. 95134, Tel 408.943.1234, and Web site www.cadence.com, and (3) CALIBRE software available from Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oreg., 97070, Tel 503.685.7000, and Web site www.mentor.com.
Tolerances for the process that is to be used to fabricate the IC chip are often specified in the form of xe2x80x9crulesxe2x80x9d that are used by the layout verification tool to confirm that a chip""s design can be manufactured by the process (in an operation called xe2x80x9cdesign rule checkxe2x80x9d (DRC)). Examples of DRC rules to be used in checking an IC design include minimum width, minimum spacing between elements of a circuit, minimum width of notches, checks for acute angles and self-intersecting polygons, and enclosure and overlap checks. Such DRC rules can be applied to actual layers that are to be fabricated in the chip. Such DRC rules can also be applied to layers (called xe2x80x9cderived layersxe2x80x9d) that are formed by logical operations (such as not, and, or, and xor) on actual or derived layers or some combination thereof, as described in, for example, pages 164-166 of a book entitled xe2x80x9cPrinciples of CMOS VLSI Design, A Systems Perspective,xe2x80x9d second edition, by Neil H. E. Weste and Kamran Eshraghian, published by Addison-Wesley Publishing Company that is incorporated by reference herein in its entirety.
Such DRC rules may be supplied by the user through a graphical user interface (GUI), such as xe2x80x9ccomposerxe2x80x9d included in software called xe2x80x9cdw-2000xe2x80x9d available from Design Workshop Inc., 7405 Trans-Canada, Suite 320, St-Laurent, Quxc3xa9bec, Canada H4T IZ2, Web site www.designw.com. DRC rules are normally stored in a computer file commonly called a xe2x80x9crunsetxe2x80x9d (also called xe2x80x9crule set,xe2x80x9d xe2x80x9crule file,xe2x80x9d xe2x80x9crule deck,xe2x80x9d or xe2x80x9crule scriptsxe2x80x9d). The runset is supplied as input to the layout verification tool to check if a design conforms to the DRC rules in the runset. The DRC rules are commonly expressed in a computer language that is specific to each layout verification tool (such as the xe2x80x9cStandard Verification Rules Formatxe2x80x9d (SVRF) used by CALIBRE, as described at Web site www.mentor.com/calibre/datasheets/calibre/index.html). According to Mentor Graphics, an SVRF optimizing compiler automatically tunes the order and type of operations performed during verification. These optimizations include eliminating redundant steps and combining similar operations into parallel computations.
Moreover, Mentor Graphics states at the above-described web site that an xe2x80x9cautomatic rule deck converterxe2x80x9d enables designers to get started right away, taking advantage of their existing rule decks. Such converters normally convert from the native language of one layout verification tool to the native language of another layout verification tool, thereby to allow the user to switch tools. Other such converters include utilities named A2drc (that translates the design rules from a Milkyway database to a Hercules DRC runset file) and A21vs (that translates netlist information from a Milkyway database to a Hercules LVS runset file) which are available in the HERCULES software (described above).
A method in accordance with the invention automatically specifies a unique number of an error layer for each DRC rule in a runset. Therefore, all errors related to a given DRC rule are reported by a layout verification tool in the specified error layer, and so all errors can be viewed by simply turning off a display of other layers in a schematic editor. Furthermore, in one embodiment, the method also automatically specifies a unique number of a filter layer that has the same extent as a quality assurance (QA) cell, and the filter layer can be logically operated (e.g. ANDed) with the error layer to uniquely identify a failure related to the DRC rule being checked. The use of unique error and filter layers eliminates spurious errors that are normally generated by QA cells designed to test other DRC rules, but which end up violating the DRC rule being checked.
QA cells of the type described above can be generated automatically by use of a template, which is identified by the user from among a library of templates (either through a set of commands that define the QA cell in a meta language, or through a graphical user interface, or some combination thereof). The template can be implemented as a macro definition or as a function in a high level programming language. Use of such templates allows automatic generation of QA cells, and so QA cell development and maintenance efforts are dramatically reduced. Moreover, regression testing using QA cells is simplified. Furthermore, template-generated QA cells are easily regenerated when layers or rules change. Also, such QA cells have a consistent appearance. Moreover, template-generated QA cells can be written in xe2x80x9cstreamxe2x80x9d format, thereby enabling the cells to be merged into QA cell libraries containing other, more complex test data.
In a regression testing method in accordance with the invention, the first time a runset is run against a test design or QA cell library the results are manually verified and stored as xe2x80x9cexpectedxe2x80x9d results. Thereafter when the runset changes or a new version of the verification tool becomes available the test data may be used to identify any differences in the results. Specifically, the regression testing method graphically compares the new test results with the expected results and highlights the differences.
The graphical comparison can be performed by a utility that automatically compares a first set and a second set of shapes. Each shape in the two sets is defined in a record having a field that identifies the type of shape (examples include circle, polygon, wire and boundary), and a list of one or more points, each point having two coordinates (e.g. x,y coordinates of the origin of a circle, or of one point in a polygon). The utility uses a hash function (e.g. simply add up all the coordinates in a list), to generate a hash number, and the records are indexed by their hash number. Thereafter, for each shape in the first set, the utility looks up shapes in the second set that have identical hash numbers, and then compares records in the two sets to confirm that the shapes are identical.
Such an automated comparison eliminates the possibility of human error associated with reviewing large quantities of test results. The test review time is dramatically reduced, because the user can focus on the differences between the two groups of shapes (which may be displayed in different colors, for example). Moreover, in one implementation, xe2x80x9cstreamxe2x80x9d format is used to avoid dependence on specific tools.